Abstract: While silicon scaling has reached astonishing levels over the last half century, there has not been a corresponding level of scaling in electronic packaging technology. However, Artificial Intelligence (AI) architectures are now changing the landscape, increasingly moving us towards chiplets and advanced packaging technology, especially Heterogeneous Integration (HI). What are these unique requirements of AI that are driving the need for HI? What are some of the unique challenges in semiconductor and packaging technologies that must be overcome to make this successful? This seminar will discuss key HI methods including interposers, fan out wafer level processing, silicon bridges, and 3D integration. We will look at their attributes as well as their challenges, to determine how they can be leveraged to achieve AI architectures.
Presenter: Dr. Mukta Farooq, IEEE EDS Distinguished Lecturer
Bio: Dr. Mukta Farooq is an IBM Distinguished Research Scientist and the 3D Integration Technology Leader for the AI Hardware Center at IBM Research. She is an IEEE Fellow, an IEEE Electron Device Society Distinguished Lecturer, and a Distinguished Alumna of IIT-Bombay
(India). Mukta is a metallurgist and materials scientist with expertise in Heterogeneous Integration for Chiplet Technology, TSV Integration in CMOS Back End of Line, Lead-free Alloys, and Chip Package Interaction. She has 245 granted US patents, 66 granted international
patents, and is an IBM Lifetime Master Inventor and IBM Academy of Technology member. She has been invited to give keynote/plenary talks at ASMC, DPS, others, and to teach short courses at IEDM, VLSI, EDTM.
Mukta received her BS from IIT-Bombay, MS from Northwestern University, and PhD from Rensselaer Polytechnic Institute.
