Advancements in technology scaling have ushered in larger systems boasting enhanced functionality, increased operational speed, and expanded data bandwidth. However, these benefits come with more demanding clocking requirements, including extended distribution distances and heightened timing precision. Furthermore, technology scaling has rendered traditional analog design challenging. Wider PVT variations necessitate intensive calibration efforts, and increased integration levels call for resilience against external noise sources. Moreover, the fact that reference frequency and loop bandwidth do not scale at the same rate as technology leads to prohibitive costs for oversized loop filters. While pure analog implementations offer intuitive operation and elegant analysis, clocking circuits incorporating digital elements offer effective solutions to these challenges.
This presentation will cover how digital circuits can enhance clock generation and distribution through techniques like calibration and signal processing. Beginning with well-established methods that harness the mixed-signal nature of PLLs, such as delta-sigma modulation for the MDD in fractional-N PLLs, the presentation will shift toward digital-intensive architectures. It will focus on techniques that leverage digital implementations for error detection and enhance timing accuracy through either analog or digital correction. State-of-the-art designs featuring runtime calibration and power noise cancellation for clock generation and distribution will also be introduced. This talk will conclude with insights into future challenges and trends.
Speaker(s): , Ping-Hsuan Hsieh
Agenda:
8pm – 9pm : DL and Q/A
Virtual: https://events.vtools.ieee.org/m/420963
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